1. Field of the Invention
The present invention relates to a differential amplifier circuit for use in a semiconductor integrated circuit, and, more particularly, to a differential amplifier circuit used in a comparator circuit and an operational amplifier (hereafter abbreviated as "op amp") circuit.
2. Description of the Related Art
Referring to FIG. 1, a conventional op amp circuit 10 formed by MOS transistors shown. The op amp circuit 10 has first and second inputs Vin1, Vin2 and an output Vout. The output Vout is connected to the second input Vin2. In the op amp circuit 10, when an input signal Vin1 is at a higher level than an input signal Vin2 or an output signal Vout, the potential at a node N1 is reduced to decrease a drain current from a transistor Tr7, resulting in a decrease in the drain current from a transistor Tr10, which in turn increases the voltage level of the output signal Vout at an output terminal To.
On the other hand, when the input signal Vin1 is at a lower level than the input signal Vin2, the potential at the node N1 rises, which increases the drain current from the transistor Tr7, resulting in an increase in the drain current from the transistor Tr10, which reduces the voltage level of the output signal Vout at the output terminal To.
In this manner, the op amp circuit 10 operates to bring the voltage levels of both signals Vin1 and Vout substantially into coincidence with each other through the feedback of the output signal Vout. More specifically, a current source 1 supplies a constant current to the drain of an N-channel MOS transistor Tr1. Transistors Tr1, Tr2 have their gates connected together. The drain of the transistor Tr1 is connected to the gates of the transistors Tr1, Tr2. Both of the sources of the transistors Tr1, Tr2 are connected to the ground GND. Thus, the transistors Tr1, Tr2 form a current mirror circuit.
P-channel MOS transistors Tr3, Tr4 have sources connected to a power supply Vcc and gates connected to a drain of the transistor Tr3. The gates of the transistor Tr3, Tr4 are connected to each other. The drain of the transistor Tr3 is connected to the drain of the transistor Tr2. The transistors Tr3, Tr4 also form a current mirror circuit. The transistor Tr4 operates as a constant current source which passes a drain current equal to the current flow through the current source 1.
The drain of the transistor Tr4 is connected to the sources of P-channel MOS transistors Tr5, Tr6. The transistor Tr5 has a drain connected to the drain of the N-channel MOS transistor Tr7. The source of the transistor Tr7 is connected to the ground GND.
The drain of the transistor Tr6 is connected to the drain of an N-channel MOS transistor Tr8 and also connected to the gates of the transistors Tr7, Tr8. The transistor Tr8 has a source connected to the ground GND. The transistors Tr5, Tr6 have gates for receiving input signals Vin1, Vin2, respectively. Thus, the transistors Tr5 to Tr8 form a differential input circuit which is activated by the constant current supplied from the transistor Tr4.
The N-channel MOS transistor Tr10 has a gate connected to the drains of the transistors Tr5, Tr7, a drain connected to the power supply Vcc via a P-channel MOS transistor Tr9, and a source connected to the ground GND. The node N1 is defined as the junction between the transistors Tr5, Tr7 and Tr10.
The transistor Tr9 has a gate connected to the gates of the transistors Tr3, Tr4. A drain current which is the same as the drain currents from the transistors Tr3, Tr4 passes through the transistor Tr9 as an idling current.
The drain of the transistor Tr10 is connected to the output terminal To for the output signal Vout of the op amp circuit. The output signal Vout is fed back to the gate of the transistor Tr6.
Referring to FIG. 2, a second prior art op amp circuit 20 is shown The op amp circuit 20 includes the op amp circuit 10 of FIG. 1, to which a circuit 22 formed by N-channel MOS transistors Tr11 and Tr14 and P-channel MOS transistors Tr12, Tr13 and Tr15 is added. The added circuit 22 controls the drain current of the transistor Tr9 on the basis of the potential on the node N1.
The transistor Tr11 has a gate connected to the node N1, a source connected to the ground GND and a drain connected to the drain of the transistor Tr12 and to the gates of the transistors Tr12, Tr13. The transistors Tr12, Tr13 each have a source connected to the power supply Vcc. The transistors Tr12 and Tr13 form a current mirror circuit which passes a drain current equal to that of the transistor Tr11.
The transistor Tr14 has a drain connected to the drain of the transistor Tr13, a source connected to the ground GND and a gate connected to the gates of the transistors Tr1 and Tr2. Accordingly, the drain current from the transistor Tr14 is a constant current which is equal to the drain current from each of the transistors Tr1 and Tr2.
The transistor Tr15 has a drain connected to the drain of the transistor Tr14 and to the gates of the transistors Tr15 and Tr9, and a source connected to the power supply Vcc.
In the op amp circuit 20, the potential at the node N1 is reduced when the level of the input signal Vin1 is higher than that of the input signal Vin2, thereby resulting in a decrease in the drain current from the transistor Tr10, which reduces the drain current from the transistor Tr11 and also the drain currents from the transistors Tr12 and Tr13, and reduces the drain current from the transistor Tr15. As a consequence, the drain current from the transistor Tr9 increases, increasing the voltage level of the output signal Vout.
On the other hand, when the level of the input signal Vin1 is lower than that of the input signal Vin2, the potential at the node N1 rises, with a consequent increase in the drain current from the transistor Tr10. The drain current from the transistor Tr11 then increases, which in turn increases the drain currents from the transistors Tr12, Tr13, thus decreasing the drain current from the transistor Tr15. Consequently, the drain current from the transistor Tr9 decreases, reducing the voltage level of the output signal Vout.
In this manner, the transistors Tr7 and Tr10 operate in a push-pull mode in accordance with a change in the potential at the node N1 so as to bring the voltage levels of the input signal Vin1 and the output signal Vout substantially into coincidence with each other. Drain currents from the transistors Tr9, Tr10 are controlled in a manner depending on a load connected to the output terminal To, allowing an increase in the operating speed and a reduction in the power dissipation of the op amp circuit 20.
In the op amp circuit 20 described above, an offset voltage between the input signal Vin1 and the output signal Vout occurs as a result of a difference between the gate-source voltage Vgs of the transistor Tr5 and the gate-source voltage Vgs of the transistor Tr6. When the transistors Tr5 and Tr6 have an equal size, a difference in the gate-source voltage is caused by differences in the drain-source voltage and the drain current.
The drain voltage of the transistor Tr6 is determined by the gate-source voltage of the transistor Tr8, which is in turn determined by the magnitude of the current distributed by the transistor Tr4 to the transistors Tr5, Tr6. The magnitude of the current varies in a range from "0" to the drain current of the transistor Tr4.
On the other hand, the drain voltage of the transistor Tr5 is determined by the gate-source voltage of the output transistor Tr10, which is in turn determined by the drain voltage and the drain current of the output transistor Tr10. The drain voltage of the transistor Tr10 or the output voltage Vout undergoes a large variation in a range between the supply voltage Vcc and the ground GND. The drain current of the transistor Tr10 also undergoes a large variation in a range between "0" and the maximum drain current of the transistor Tr10, depending on a load connected to the output terminal To.
There is no correlation between factors which determine the respective drain voltages of the transistors Tr5, Tr6 which form the input differential pair. This causes a difference in the drain-source voltage to be produced between the transistors Tr5, Tr6, with resulting differences in the drain current and the gate-source voltage between both of the transistors Tr5, Tr6. This explains the occurrence of the offset voltage between the input signal Vin1 and the output signal Vout.
The offset voltage could be eliminated by adjusting the load condition such that the gate-source voltage is substantially equal for each of the transistors Tr8 and the transistor Tr10, but it is actually difficult to eliminate the offset voltage by constraining a load fluctuation within a given range.
The offset voltage does not remain constant for a change in the input signal, and thus the output signal does not follow the change in the input signal, presenting a problem that a linear input-output response cannot be obtained.
It is an object of the present invention to provide a differential amplifier circuit which suppresses the occurrence of an offset voltage between an input and an output and for providing a linear input-output response.